Fascination About Anti-Tamper Digital Clocks
Fascination About Anti-Tamper Digital Clocks
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Another facet of the invention might reside in an equipment for detecting clock tampering, comprising a circuit that gives a monotone signal, a plurality of resettable delay line segments, and an evaluate circuit. The circuit delivers the monotone sign throughout a clock Consider period of time associated with a clock. The plurality of resettable hold off line segments delay the monotone signal to generate a respective plurality of delayed monotone indicators.
usually means for delaying the monotone signal to generate a plurality of delayed monotone signals getting discretely rising delay periods involving a minimum delay time as well as a utmost hold off time and each in the plurality of delayed monotone signals obtaining both a 1 or maybe a zero logic price;
a second plurality of resettable hold off line segments that every delay the second monotone sign to deliver a respective next plurality of delayed monotone alerts, wherein resettable hold off line segments involving a resettable delay line phase connected with a minimum delay time along with a resettable hold off line segment related to a highest hold off time are Just about every linked to discretely escalating hold off situations; and
An element of the current invention could reside in a technique for detecting voltage tampering. In the strategy, a plurality of resettable delay line segments are provided. Resettable delay line segments in between a resettable delay line segment connected to a minimum amount delay time in addition to a resettable hold off line segment associated with a most hold off time are Every connected with discretely growing hold off occasions.
The 2nd circuit supplies a 2nd monotone sign throughout a second clock Assess period of time linked to the clock. The second clock Consider time frame covers another time than the main clock Consider time period. The 2nd plurality of resettable delay line segments Each individual hold off the main monotone sign to crank out a respective next plurality of delayed monotone alerts. Resettable delay line segments between a resettable hold off line segment connected with a bare minimum hold off time as well as a resettable hold off line section affiliated with a optimum hold off time are Just about every connected to discretely rising hold off moments. The Consider circuit is induced with the clock and takes advantage of the first plurality of delayed monotone signals or the next plurality of delayed monotone indicators to detect a clock fault.
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Disclosed is a method for detecting clock tampering. In the strategy a plurality of resettable delay line segments are furnished. Resettable hold off line segments involving a resettable delay line segment related to a minimum delay time along with a resettable delay line segment connected with 9roenc LLC a most delay time are each related to discretely raising hold off situations.
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eleven. The apparatus for detecting clock tampering as described in claim 8, whereby-the usually means for evaluating determines no matter if the quantity of types from the plurality of delayed monotone signals differs from a drinking water degree variety by in excess of a predetermined threshold.
Yet another aspect of the invention may well reside within an apparatus for detecting clock tampering, comprising: indicates 250 for supplying a monotone sign 220 for the duration of a clock Assess time frame 310 associated with a clock CLK; means 210 for delaying the monotone sign utilizing a plurality of resettable hold off line segments to deliver a respective plurality of delayed monotone indicators 230 having discretely expanding delay moments in between a minimal hold off time as well as a most delay time; and signifies 240 for utilizing the clock CLK to set off an Consider circuit 240 that uses the plurality of delayed monotone signals to detect a clock fault.
eighteen. The apparatus for detecting clock tampering as outlined in declare fifteen, wherein the Consider circuit decides no matter whether the quantity of ones while in the plurality of delayed monotone indicators differs from a water degree selection by in excess of a predetermined threshold to detect a clock fault.